TSMC’s N2 Expertise – IEEE Spectrum

TSMC described its next generation transistor technology this week at the IEEE International Electron Device Meeting (IEDM) in San Francisco. The N2, or 2-nanometer, technology is the semiconductor foundry giant’s first foray into a new transistor architecture, called nanosheet or gate-all-around.

Samsung has a process for manufacturing similar devices, and both Intel and TSMC expect to be producing them in 2025.

Compared to TSMC’s most advanced process today, N3 (3-nanometer), the new technology offers up to a 15 percent speed up or as much as 30 percent better energy efficiency, while increasing density by 15 percent.

N2 is “the fruit of more than four years of labor,” Geoffrey YeapTSMC vice president of R&D and advanced technology told engineers at IEDM. Today’s transistor, the FinFET, has a vertical fin of silicon at its heart. Nanosheet or gate-all-around transistors have a stack of narrow ribbons of silicon instead.

The difference not only provides better control of the flow of current through the device, it also allows engineers to produce a larger variety of devices, by making wider or narrower nanosheets. FinFETs could only provide that variety by multiplying the number of fins in a device—such as a device with one or two or three fins. But nanosheets give designers the option of gradations in between those, such as the equivalent of 1.5 fins or whatever might suit a particular logic circuit better.

Called Nanoflex, TSMC’s tech allows different logic cells built with different nanosheetwidths on the same chip. Logic cells made from narrow devices might make up general logic on the chip, while those with broader nanosheets, capable of driving more current and switching faster, would make up the CPU cores.

The nanosheet’s flexibility has a particularly large impact on SRAM, a processor’s main on-chip memory. For several generations, this key circuit, made up of 6 transistors, has not been shrinking as fast as other logic. But N2 seems to have broken this streak of scaling stagnation, resulting in what Yeap described as the densest SRAM cell so far: 38 megabits per square millimeter, or an 11 percent boost over the previous technology, N3. N3 only managed a 6 percent boost over its own predecessor. “SRAM harvests the intrinsic gain of going to gate-all-around,” says Yeap.

Future Gate-All-Around Transistors

While TSMC delivered details of next year’s transistor, Intel looked at how long industry might be able to scale it down. Intel’s answer: Longer than originally thought.

“The nanosheet architecture actually is the final frontier of transistor architecture,” Ashish Agrawala silicon technologist in Intel’s components research group, told engineers. Even future complementary FET (CFET) devices, possibly arriving in the mid-2030s, are constructed of nanosheets. So it’s important that researchers understand their limits, said Agrawal.

“We have not hit a wall. It’s doable, and here’s the proof… We are making a really pretty good transistor.” —Sanjay Natarajan, Intel

Intel proved that a transistor with a 6-nanometer gate length works well.Intel

Intel explored a critical scaling factor, gate length, which is the distance covered by the gate between the transistor’s source and drain. The gate controls the flow of current through the device. Scaling down gate length is critical to reducing the minimum distance from device to device within standard logic circuits, called called contacted poly pitch, or CPP, for historical reasons.

“CPP scaling is primarily by gate length, but it’s predicted this will stall at the 10-nanometer gate length,” said Agrawal. The thinking had been that 10 nanometers was such a short gate length that, among other problems, too much current would leak across the device when it was supposed to be off.

“So we looked at pushing below 10 nanometers,” Agrawal said. Intel modified the typical gate-all-around structure so the device would have only a single nanosheet through which current would flow when the device was on.

By thinning that nanosheet down and modifying the materials surrounding it, the team managed to produce an acceptably performing device with a gate length of just 6 nm and a nanosheet just 3 nm thick.

Eventually, researchers expect silicon gate-all-around devices to reach a scaling limit, so researchers at Intel and elsewhere have been working to replace the silicon in the nanosheet with 2D semiconductors such as molybdenum disulfide. But the 6-nanometer result means those 2D semiconductors might not be needed for a while.

“We have not hit a wall,” says Sanjay Natarajansenior vice president and general manager of technology research at Intel Foundry. “It’s doable, and here’s the proof… We are making a really pretty good transistor” at the 6-nanometer channel length.

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